(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method that eliminates edge peeling during Chemical Mechanical Polishing of a layer of low-k dielectric material.
(2) Description of the Prior Art
One of the concerns of creating semiconductor devices relates to the creation or maintenance of good surface planarity of layers of semiconductor material as part of the created semiconductor devices. One of the more frequently applied layers of semiconductor material for the creation of semiconductor devices comprises a dielectric material that typically is used as a layer of insulation between for instance metal interconnects of a semiconductor device.
In fabricating semiconductors, surface planarity of a semiconductor wafer and of thereover deposited layers of semiconductor material must be maintained to meet requirements of optical projection lithography. Good surface planarity is crucial to the lithography process, since consistent and uniform depth of focus of the lithography process cannot be provided for surfaces that do not have good planarity.
A frequently applied method of maintaining or establishing surface planarity is the process of Chemical Mechanical Polishing (CMP) of the surface that is planarized. Chemical Mechanical Polishing is a method of polishing materials, such as semiconductor substrates or layers of dielectric, to a high degree of planarity and uniformity. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry over the substrate.
A typical CMP process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing together with a positioning member, which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may include abrasive materials, is deposited over the surface of the polishing pad to modify the polishing characteristics of the polishing pad, thereby enhancing the polishing action of the substrate.
In the conventional approach, the wafer is held over a circular carrier, which rotates. The polishing pads, made from a synthetic fabric, are mounted over a polishing platen, which has a flat surface, the polishing platen rotates. The rotating wafer is brought into physical contact with the rotating polishing pad, an action that constitutes the Chemical Mechanical Polishing process. Slurry, which typically includes pH-balanced chemicals, such as sodium hydroxide and silicon dioxide particles, is dispensed onto the polishing pad, typically using a peristaltic pump, excess slurry typically goes to a drain.
Polishing is frequently used in applications where, in applying the CMP process to layers of dielectric material such as Intra-Level Dielectric (ILD) and Inter Metal Dielectric (IMD) that are used for the manufacturing of semiconductor wafers, surface imperfections or micro-scratch present a problem. Imperfections caused by micro-scratches in the ILD and IMD can range from 100 to 1,000 EA for 200 mm wafers, where an imperfection typically has a depth from 500 to 900 A0 and a width of from 1,000 to 3,000 A0.
Of the dielectric materials that are used for the creation of semiconductor devices, low-k dielectrics are preferred since this dielectric provides advantages of device performance. In polishing the surface of a layer of low-k dielectric, it is not uncommon to experience problems of edge peeling of the polished layer, resulting in wafer loss due to the process of CMP. The invention addresses this concern by making use of the observation that dense low-k dielectric material has superior resistance to polishing by CMP than porous (less dense) low-k dielectric. By therefore covering a layer of relatively porous low-k dielectric with a layer of relatively dense low-k dielectric and by polishing the surface of the dense layer of low-k dielectric, the conventional problems of edge peeling encountered when polishing a porous low-k layer of dielectric can be counteracted. It must thereby be appreciated that the terms “porous” and “dense” are relative to each other.
U.S. Pat. No. 5,618,380 (Siems et al.) shows a wafer edge sealing process.
U.S. Pat. No. 5,952,050 (Doan) shows a method to remove material from the wafer edge.
U.S. Pat. No. 6,303,899 B1 (Johnson et al.) and U.S. Pat. No. 6,057,206 (Nguyen et al.) are related patents.